analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents

Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

code coverage , System Verilog, Cover groups, Functional coverage, Assertions, DDR4, Uvm, DIMM, DDR5

Bug Tracking Tool, System Verilog, C, Git, Synopsys, Cadence, RTL simulations

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

System Verilog, Verilog, SoC Verification, Design Verification, Uvm, Asic verification