Tcp Ip, Perl, Pcie, Ethernet, Shell scripting, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, Verilog RTL design, networking IP solutions, Design for Test methodologies, DMAs, NVMe based Storage IP

Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools

Shell, Tcl, Perl, DMA, digital design fundamentals, control data path logic, protocol bridges, low-power design flows, systemverilog, power performance and area optimization techniques, lint CDC RDC synthesis STA constraints, RTL design using Verilog, memory-mapped peripherals, micro-architecture definition, Dft, bus fabrics, debugging skills for simulation synthesis and integration issues

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Tcp Ip, Shell scripting, Ethernet, Perl, Pcie, RDMA IPs, Design for Test methodologies, NVMe based Storage IP, Verilog RTL design, Silicon IP development process methodologies, VCS simulation tool, DMAs

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

RDC, RTL coding expertise in Verilog, SpyGlass Lint, micro-architecture development, systemverilog, FSM design, Pipelining techniques, ASIC SoC design flow, Datapath architecture, cdc, Clock and Reset domain crossings

Perl, Verilog, Tcl, Python, VHDL, AXI Protocols, Ethernet protocol, Ethernet IPs, Rtl Design