Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Pcie, SV, CXL, PCI-E, LPDDR, UCIe, DDR4, Uvm, USB 3.0

Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures