boundary scan , Scripting, Debugging, Programming, Perl, Python, Tcl, Scan Insertion, MBIST, DFT methodologies, ATPG, Repair logic

memory test , Scripting Languages, Digital Logic Design, Hdl, Jtag, Static Timing Analysis, IEEE1500, BIST Architecture, Compression Techniques, IEEE1149.1, Eco, ASIC, Logic Design Flow, Scan ATPG, Gates Verification, Simulation

Unix, Linux Os, Verilog, Tcl, Ruby, Jtag, Python, Perl, Scripting Languages, SV, MBIST, IO-PHY loopback testing, systemverilog, DFT feature verification, file version control, EDA simulation tools, Cadence NCSIM, UVM verification methodologies, Verdi, SVA, Synopsys VCS, fuse, Scan, debug tools

Tcl, Jtag, Awk, Sed, LBIST, MBIST, gate-level simulation, Scan, ATPG, Dft, Spyglass-DFT, Tessent

logic bist , C, Verilog, Tcl, Jtag, Python, Perl, SAF, BSCAN, SDF annotated gate level verification, IEEE1149.1, Scan Codec insertion, ATPG, ATPG Fault models, Fault Simulation, PDT, VHDL, IEEE1687, Scan and Memory Diagnosis, TDF, SDD, Memory BIST and Repair implementation