Tcl, Jtag, Awk, Sed, Scan, MBIST, coverage correlation, gate-level simulation, ATPG pattern generation, Post-silicon bring up, ATPG, Scan-stitching, Spyglass-DFT, Tessent ATPG mentor, Debug skills, Scan Insertion, Test cost reduction analysis, ATPG patterns verification, Scripting skills, MBIST BISR implementation, LBIST, Tessent flow

memory test , Scripting Languages, Digital Logic Design, Hdl, Jtag, Static Timing Analysis, IEEE1500, BIST Architecture, Compression Techniques, IEEE1149.1, Eco, ASIC, Logic Design Flow, Scan ATPG, Gates Verification, Simulation