Senior DFT Engineer

About the Company

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and healt

h.

The Cadence Advan

• tage
  
  The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an i
• mpact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the empl
• oyees.The unique One Cadence – One Team culture promotes collaboration within and across teams to ensure customer su
• ccess.Multiple avenues of learning and development available for employees to explore as per their specific requirement and inte
• rests.You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—ever

y day.

About

the Role

Job respons

ibilities:

Resp

• onsibilities
  
  BE/BTECH/ME/MTECH Or Equ
• ivalent DegreeEXP-2-6years equivale
• nt or RelevantVery good knowledge on SCAN/A
• TPG/JTAG/MBISTExperience with one or more chip tape out that includes chip
• ATE bring up.Experience on gate level simulation with no timing and timing (SDF) simulations (AT
• PG/MBIST/JTAG)Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improveme
• nt techniques.Experience in scan insertion techniques at block level and c
• hip top level.Experience on Memory BIST generation, insertion, verification on RTL/
• Netlist level.Good knowledge and understanding in Analog PHY and Analo
• g Macro tests.Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE114
• 9.6 standards.Good knowledge on test mode timin
• g constraints.Good knowledge about running block level and c
• hip STA flows.Cross domain knowledge to resolve DFT issues with design, synthesis, physical des
• ign, STA team.Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/T
• essent tools).Experience with post-silicon bring up and
• debug on ATE.Good knowledge on Perl/Tcl scr
• ipting skills.Very good team player capabilities and excellent communication skills to work with a variety of teams across the global
• organization.High sense of responsibility and ownership within the team for successful tape out and post-silicon bring
• up of project.Should have B-Tech/M-tech with 2 Years to 5 Years releva

nt experience.

Qualifications

BE/BTECH/ME/MTECH Or

Equivalent Deg

• ree
  
  Required Skills
  
  Very good knowledge o
• n SCAN/ATPG/JTAG/MBISTExperience with one or more chip tape out that inclu
• des chip ATE bring up.Experience on gate level simulation with no timing and timing (SDF) simulat
• ions (ATPG/MBIST/JTAG)Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage i
• mprovement techniques.Experience in scan insertion techniques at block lev
• el and chip top level.Experience on Memory BIST generation, insertion, verification
• on RTL/Netlist level.Good knowledge and understanding in Analog PHY a
• nd Analog Macro tests.Good knowledge and understanding on JTAG for IEEE 1149.1
• /IEEE1149.6 standards.Good knowledge on test mo
• de timing constraints.Good knowledge about running block lev
• el and chip STA flows.Cross domain knowledge to resolve DFT issues with design, synthesis, phys
• ical design, STA team.Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable C
• adence/Tessent tools).Experience with post-silicon brin
• g up and debug on ATE.Good knowledge on Perl
• /Tcl scripting skills.Very good team player capabilities and excellent communication skills to work with a variety of teams across th
• e global organization.High sense of responsibility and ownership within the team for successful tape out and post-silico

n bring up of pr

oject.

Preferred Skills

Should have B-Tech/M-tech with 2 Years to 5

Years relevant experience.

Pay ra

nge and compen