C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Physical Design Planning, Placement, Floor Planning

Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout