NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, MemView Generation, PVT Corner Coverage, LEF

Routing, DDR design knowledge, floorplanning, Calibre, primetime, Innovus, RTL-to-GDSII implementation, Placement, EDA Tools, Genus, Tcl tool scripting, Physical Design Methodologies, MultiTap-CTS

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Physical Design, Physical Design Engineer, Automation script

Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, NDM Liberty, MemView Generation, LEF, PVT Corner Coverage

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, MemView Generation, LEF, PVT Corner Coverage

Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus