shielding , Custom layout design, Clock routing, Signal flow optimization, Power ground routing methodologies, Parasitic RC minimization, Mentor Graphics, EM IR analysis, Cadence Virtuoso, Device matching, Biasing strategies

shielding , Custom layout design, Clock routing, Signal flow optimization, Power ground routing methodologies, Parasitic RC minimization, Mentor Graphics, Cadence Virtuoso, EM IR analysis, Device matching, Biasing strategies

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters

Linux, Perl, Python, Tcl, EM, LVS, IR analysis, Calibre, physical signoff flows, ERC, DRC, Parasitic Extraction, Cadence Virtuoso

Linux, Perl, Python, Tcl, EM, LVS, IR analysis, Calibre, ERC, physical signoff flows, DRC, Parasitic Extraction, Cadence Virtuoso

Linux, Tcl, Python, Perl, Calibre, physical signoff flows, LVS, EM, Parasitic Extraction, Cadence Virtuoso, ERC, DRC, IR analysis