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Experience - 7+years
Location - Pan India
NP - Immediate to 60 Days
JD Design Verification
Job ID: 145265765
Skills:
analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis
Skills:
scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents
Skills:
Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB
Skills:
DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog
Skills:
code coverage , System Verilog, Cover groups, Functional coverage, Assertions, DDR4, Uvm, DIMM, DDR5
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