Senior Design Verification Engineer
Senior Design Verification Engineer
Globex Digital CorpEarly Applicant
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Experience - 7+years
Location - Pan India
NP - Immediate to 60 Days
JD Design Verification
- Understanding the business requirements and functional specifications of the IPs, subsystems and SOC
- Creating Verification Environment Architecture document
- Reviewing and Revising: working towards meeting agreed upon acceptance criteria
- Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification
- Performing RTL simulations using Synopsys and Cadence simulators
- Debugging and resolving problems found by simulations .Performance test plan development and maintenance
- Development of transactors, monitors and models for performance verification.
- Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms
- Provide full report of performance metrics and bottlenecks
- Tracking tickets and code releases using Bug Tracking tool and GIT
- Performing UPF (Unified Power Format) based Power Aware simulations
- Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)
- Code & Functional Coverage Closure
- Performing Gate Level simulations .Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality
More Info
Key Skills
Models for performance verification
Monitors
Transactors
Performance test plan development
RTL simulations
About Company
Skills:
Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling
Skills:
Nvme, Pcie, Ethernet, System Verilog, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB
Skills:
ASIC design flow, C Assertions coding, ARM based SOC software framework, Analog-Digital Interface, WREAL AMS model, SV-UVM, UVM assertion based coverage driven verification, constraint random test generation, multi-core multi-layer APIs, functional coverage, ARM processor based SoC architecture, ASIC verification methodologies