Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC

Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Multi-Mode and Multi-corner designs, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Floor Planning, ASIC Physical implementation, Global signal planning, Physical convergence

Advanced PowerPoint, Storytelling Structure, Analytical and Problem-Solving Skills, Design Thinking, Stakeholder Management

Pcie, Verilog, Networking Protocols, Static timing analysis, Timing closure methodologies, RDC analysis, RTL implementation, Synthesis, AMBA-AXI, Power methodology development, systemverilog

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

ASIC development cycle, ASIC design methodologies, develop solutions, cross-functional teams, Rtl Design, architecture, Verification