ASIC Engineer, Design
- Posted 19 days ago
- Be among the first 50 applicants
Job Description
Meta is looking for ASIC Engineer, Design to join our dynamic team and embark on a rewarding career journey.
- Develop and implement ASIC design methodologies, including design, verification, and testing
- Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs
- Develop and maintain design specifications, test plans, and documentation
- Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis
- Perform design optimization and analysis to ensure optimal performance and power efficiency
- Ensure compliance with industry standards and guidelines.
- Strong knowledge of ASIC design methodologies and tools.
- Excellent communication and interpersonal skills Strong analytical and problem-solving skills
More Info
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Key Skills
ASIC development cycle
ASIC design methodologies
develop solutions
cross-functional teams
About Company
Skills:
Verilog, System Verilog, FPGA tools, Synthesis, formal property verification, timing constraints development, RTL Coding, assertions, uArch, CDC checks
Skills:
Vcs, programming, Scripting, Python, System Verilog, Asic verification, NCSim, verification of HBM memory interfaces, UVM testbench development, verification of SerDes IP block interfaces, Modelsim, formal model equivalence checking
Skills:
finishes, Digital tools, Email, Architecture, Spreadsheets, Interior materials, Furniture, Interior Design, crm software, Design concepts
Skills:
UNIX, Verilog, Debugging, design quality checks, SoC connectivity concepts, Simulation, RTL integration, Digital Design, Windows environments, systemverilog, RTL Coding, Ms Office Tools, ASIC SoC design methodologies
Skills:
test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN