Physical Design Lead
Physical Design Lead
Mirafra Technologies5-7 Years
- Posted 40 minutes ago
- Be among the first 10 applicants
Job Description
We are looking for an experienced Physical Design / SoC Full-Chip Technical Lead to drive the execution, methodology, and physical closure of complex next-generation SoC designs across advanced technology nodes, including 7nm, 5nm, 3nm, and beyond.
This role offers the opportunity to lead technically challenging full-chip implementations, collaborate closely with architecture and design teams, and own the physical implementation journey from RTL/Netlist to GDSII and tape-out.
Key Responsibilities
Technical Leadership & Full-Chip Ownership
- Lead end-to-end physical implementation of complex SoCs and large sub-systems from RTL/Netlist through GDSII and tape-out.
- Provide technical leadership and mentorship to the Physical Design team.
- Drive execution, schedules, methodologies, and technical deliverables across the full-chip implementation flow.
- Partner with Architecture, RTL, DFT, STA, Power, Signal Integrity, Packaging, and Verification teams to resolve complex design challenges.
What We're Looking For
- Strong experience in full-chip Physical Design / Physical Implementation of complex SoCs.
- Proven experience working on advanced process nodes such as 7nm, 5nm, 3nm, or below.
- Strong understanding of the complete RTL-to-GDSII flow.
- Hands-on expertise in Floorplanning, Synthesis, Placement, CTS, Routing, STA, SI, DRC/LVS, and EM/IR.
- Experience with hierarchical designs, large SoCs, complex power domains, and challenging timing closure.
- Strong problem-solving and technical leadership skills.
- Ability to work effectively across multiple engineering disciplines and drive issues to closure.
- Experience mentoring engineers and leading technical execution across complex projects.
Why Join Us
- Work on next-generation SoCs using advanced semiconductor process technologies.
- Solve challenging problems across physical implementation, timing, power, and signal integrity.
- Work with highly experienced cross-functional engineering teams.
- Opportunity to influence physical design methodologies, automation, and execution strategy.
- Play a key role in delivering complex designs from concept to successful tape-out.
More Info
Key Skills
CTS
EM
Physical Implementation
RTL-to-GDSII flow
DRC
About Company
Skills:
Clock Tree Synthesis (CTS), Routing, IR/EM analysis, floorplanning, Hierarchical and flat implementation flows, Physical Verification, Cadence Innovus, Timing analysis and optimization, Signoff methodologies, Timing Closure, Low-power implementation techniques, Signal Integrity, Noise issues
Skills:
congestion management , Python, Routing, Perl, Tcl, Sta, CTS, Advanced Floorplanning, Cadence Innovus, Physical Signoff, LVS, Fusion Compiler FC, UPF, MMMC, Power Distribution Network, Antenna, Multi-voltage design implementation, Placement Optimization, EM, Physical Verification, Ir, low power design, Physical Design, Timing Closure, ECO Implementation, DRC
Skills:
power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies
Skills:
Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter