Search by job, company or skills

Meta

ASIC Engineer, Design

Save
  • Posted 2 hours ago
  • Be among the first 10 applicants
Early Applicant

Job Description

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing and data-centre networking with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

ASIC Engineer, Design Responsibilities:

  • Architecture exploration
  • Micro-architecture development and RTL coding
  • Soft and hard IP identification, selection and integration
  • Collaboration with verification and emulation teams in test plan development and debug
  • Collaboration with implementation team to close the design on synthesis, timing and power

Minimum Qualifications:

  • Bachelor's degree in Electronics and Communication, Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development
  • Experience in one of these skills: Micro-architecture and RTL development for complex control/data path and networking IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development
  • Experience with RTL coding using Verilog or System Verilog
  • Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization

Preferred Qualifications:

  • Experience in data path development
  • Experience with scripting languages (TCL, Python, Perl, Shell-scripting)
  • 6+ years of experience in silicon development
  • Experience with Power Analysis and Optimization
  • Experience in HLS (High-Level Synthesis)
  • Experience working across multiple projects
  • Experience in Networking, CPU, NOC (Network on Chip), Memory and Peripheral Subsystems
  • Experience with Synthesis, Timing Closure and Formal Verification Methodology

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

More Info

Job Type:
Industry:
Employment Type:

About Company

Job ID: 150937617

Similar Jobs

Bengaluru, India

Skills:

PerlPythonTclEmulationsystemverilogSystem Verilog Assertions

Bengaluru, India

Skills:

Scripting LanguageLinux Operating SystemLogic DesignAgile development processesVerification principlesDevOps design methodologies and toolsRTL design with Verilog or VHDL

Bengaluru, India

Skills:

routingcongestion analysisIR dropprimetimefloorplanningphysical ECO implementationphysical optimizationCadence InnovusLVSPower PlanningPhysical Verificationantenna checksCalibrePhysical DesignStarRCERCTiming ClosureDRCPlacementsign-offRTL-to-GDSIISynopsys ICC2

Bengaluru, India

Skills:

VcsGdbShellPerlVerilogPythonASIC design flowfloor-planningTiming AnalysisRtl DesignEcoDebussybring-up lab debug

Bengaluru, India

Skills:

Embedded FirmwareDigital Logic DesignJtagVerilogScripting LanguagesDVFSDCVSIEEE1500memory dumpMBISTpower management verificationscan dumpUPFC LanguageDFT architecturereliability throttling