Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

python, perl, SV test benches, Gate level simulations, SDF annotation, VMM, constrained random verification, Uvm, functional coverage, C-reference models

automation, Ovm, Tcl Scripting, Verilog, Perl, Uvm, GLS, RTL, SV, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

System Verilog, Uvm, test plan generation, environment development, SV, Functional Verification, environment planning