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BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer
12+ years of Design Verification experience with SV/UVM
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
Design Verification experience verifying complex designs and leading projects from concept to verification closure.
Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag
Job ID: 142922081
Skills:
automation, Ovm, Tcl Scripting, Verilog, Perl, test-bench development, GLS, Uvm, RTL, SV, SDF sim debug, Specman, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification
Skills:
System Verilog, Uvm, Environment Development, Design Verification, Functional Verification, Test Plan Generation
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