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12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 142944285
