Technical Manager

Technical Manager

Location-Bangalore, India

Experience: 1016 Years

About the Role

We are looking for a Technical Manager to lead the verification architecture for next-generation high-performance SoCs and PCIe IPs. This role sits at the intersection of architecture, verification methodology, and technical leadership, driving scalable verification solutions for complex silicon systems.

You will define verification strategies for PCIe Gen5/Gen6/Gen7 subsystems, architect reusable infrastructure, and lead teams responsible for delivering first-pass silicon success. This role requires deep expertise in protocol architecture, verification methodology, and large-scale SoC integration.

What You'll Do

• Own the verification architecture for complex PCIe and high-speed interconnect IPs across multiple SoC programs.
• Define and drive end-to-end verification strategy from IP to full SoC level.
• Architect scalable, reusable verification environments using SystemVerilog, UVM, and advanced verification methodologies.
• Lead verification of PCIe Gen5/Gen6/Gen7 features, including link training, equalization, advanced error handling, power management, and compliance scenarios.
• Collaborate with RTL architects, micro-architecture teams, firmware, and system teams to influence design decisions and ensure verifiability.
• Drive coverage-driven verification, debug strategy, and verification sign-off criteria.
• Establish and scale best-in-class verification infrastructure including VIP integration, scoreboards, assertions, and automation frameworks.
• Mentor and guide verification engineers and technical leads, raising the bar for engineering excellence.
• Drive cross-team technical alignment across architecture, design, verification, and silicon validation.

Minimum Qualifications

• 10+ years of experience in ASIC / SoC Design Verification
• Strong expertise in PCIe protocol architecture and verification (Gen5/Gen6/Gen7)
• Deep experience with SystemVerilog and UVM-based verification environments
• Experience architecting verification environments for complex IP or SoC subsystems
• Strong debugging experience across protocol, architecture, and RTL interactions

Preferred Qualifications

• Experience with CXL or other high-speed interconnect protocols
• Experience with verification architecture across multiple IP blocks within large SoCs
• Exposure to emulation, prototyping, or post-silicon validation flows
• Experience building scalable verification infrastructure across teams
• Prior experience in technical leadership or managing DV teams

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com