Technical Manager Design Verification

Technical Manager Design Verification

Location- Bengaluru/Hyderabad

Exp-10-18yrs

About the Role

We are seeking an experienced Technical Manager Design Verification to lead complex IP and SoC verification efforts for next-generation high-speed interconnect technologies. In this role, you will drive verification strategy, mentor high-performing engineers, and ensure first-silicon success for industry-leading PCIe Gen5/6/7 solutions powering data centers, AI accelerators, and high-performance compute platforms.

You will partner closely with architecture, design, firmware, and post-silicon teams to deliver robust, scalable verification frameworks and world-class quality.

Key Responsibilities

Technical Leadership

• Own end-to-end verification strategy for PCIe Gen5/6/7 IP and SoC-level integrations
• Architect scalable SystemVerilog/UVM-based verification environments
• Drive protocol compliance, performance, stress, and corner-case validation
• Lead root-cause debug across RTL, testbench, and system interactions

Team & Execution

• Build and mentor high-impact DV teams across IP and SoC programs
• Set technical direction, best practices, and verification methodology standards
• Manage project milestones, risk mitigation, and execution quality
• Conduct design/verification reviews and signoff readiness

Cross-Functional Collaboration

• Partner with architects to influence micro-architecture for verifiability
• Work with design teams on coverage closure and bug resolution
• Interface with post-silicon and firmware for end-to-end validation strategy

Required Qualifications

• 1018 years of experience in ASIC/SoC Design Verification
• Deep hands-on expertise with PCIe Gen5/Gen6/Gen7 protocols
• Strong experience in IP-level and full-chip SoC verification
• Expert-level proficiency in:
• SystemVerilog
• UVM methodology
• Assertions (SVA), functional coverage, constrained random testing
• Proven experience leading complex verification programs to tape-out
• Strong debugging skills across RTL, protocol, and system interactions

Preferred Qualifications

• Experience with multi-die/chiplet-based SoCs
• Performance modeling and stress testing of high-speed interfaces
• Familiarity with formal verification and emulation platforms
• Prior people management or technical lead ownership of large DV teams

What You'll Drive

• First-pass silicon success for next-gen PCIe platforms
• Scalable verification infrastructure used across multiple product families
• High-quality execution in fast-paced, high-ambiguity environments

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com