Job Requirements
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
5-7 years of professional experience in leading full-chip and block-level timing signoff for complex SOC programs across advanced technology nodes.
- Strong hands-on experience in
- MCMM timing closure
- Constraint development and validation
- ECO timing closure.
- Deep understanding of:
- Timing derates (OCV/AOCV/POCV)
- SI and Crosstalk effects
- Multi-voltage and low-power timing.
- Experience in advanced nodes (16nm/5nm/3nm)
- Experience in handling large SOC (>50M instances)
- Experience in implementation tools (IIC2/Innovus)
- Must have experience in Synopsys-Primetime, Primetime-SI, Cadence Design Systems-Tempus.
We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
- 5-7 years of professional experience in leading full-chip and block-level timing signoff for complex SOC programs across advanced technology nodes.
- Strong hands-on experience in
- MCMM timing closure
- Constraint development and validation
- ECO timing closure.
- Deep understanding of:
- Timing derates (OCV/AOCV/POCV)
- SI and Crosstalk effects
- Multi-voltage and low-power timing.
- Experience in advanced nodes (16nm/5nm/3nm)
- Experience in handling large SOC (>50M instances)
- Experience in implementation tools (IIC2/Innovus)
- Must have experience in Synopsys-Primetime, Primetime-SI, Cadence Design Systems-Tempus.
