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Job Description – Senior Synthesis Engineer (VLSI)
Experience Level :- 3yrs to 6yrs
Notice Period :- Immediate to 45 Days
Work Location :- Bangalore
Mode of Work :- WFO
Employment Type :- Permanent
Job ID: 147493989
Skills:
pipelining , Ecos, Perl, Python, Tcl, Genus Fusion Compiler, Clock gating, Design DFT, Cadence Conformal LEC, UPF, Low-power design implementation, Cadence Conformal Low Power, MCMM synthesis, Physical Synthesis, STA timing closure, Netlist delivery, Multi-clock domain designs, Synopsys DCG, Synopsys Prime Time, Synthesis methodologies, Timing Constraints, formal verification
Skills:
Synthesis tool variables, DFT Insertion
Skills:
SDF, LINT, Sta, Dft, Synthesis, cdc, primetime, MMMC, Tempus, GLS
Skills:
System Verilog, Perl scripting, Tcl Scripting, Sta, SDC, RTL, Application Engineering
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