pipelining , Ecos, Perl, Python, Tcl, Genus Fusion Compiler, Clock gating, Design DFT, Cadence Conformal LEC, UPF, Low-power design implementation, Cadence Conformal Low Power, MCMM synthesis, Physical Synthesis, STA timing closure, Netlist delivery, Multi-clock domain designs, Synopsys DCG, Synopsys Prime Time, Synthesis methodologies, Timing Constraints, formal verification

Synthesis tool variables, DFT Insertion

SDF, LINT, Sta, Dft, Synthesis, cdc, primetime, MMMC, Tempus, GLS

System Verilog, Perl scripting, Tcl Scripting, Sta, SDC, RTL, Application Engineering