Desired Skills and Experience:
- Proficiency with STA, SDC.
- Proficiency with RTL, System Verilog.
- Strong understanding of front-end EDA design methodologies.
- Strong Perl, Tcl or Python scripting skills.
- Prior experience with logic synthesis tools is required.
- Prior experience using or supporting SDC tools would be a significant plus.
- Prior experience with RTL simulation, SVA would be a plus.
- Prior experience supporting front-end EDA tools would be a plus.
- Sound communication skills, verbal and written.
- Ability to produce product requirement documents.
- BS EE/CE. 4 years experience with STA/Synthesis.
