Digital Logic Design, Scripting, LINT, cdc, Processor SoC architecture, formal equivalence, Post Silicon issue debug, ASIC tapeouts, DSP fundamentals, ECO flows

bist , Test Execution, Functional Testing, Perl, Scripting Languages, Python, Tcl, Scan Insertion, digital design concepts, ATPG, test plan development, EDA Tools, MBIST implementation, Cadence, Mentor, Synopsys

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

caliber , power optimization , Sta, floor-planning, LVS, noise analysis, Innovus, Antenna, equivalence checks, Encounter, LEC, ICC, Physical Verification, primetime, ERC, DRC, partitioning, Placement, timing and functional ECOs, Crosstalk delay analysis, Clock Tree Synthesis

System Verilog, Digital-analog interface requirements, RTL design and development, Linting, Mixed-signal design flows, RDC analysis, Coverage-driven design methodologies, Timing Constraints, Digital control logic, Synthesis and timing closure methodologies, RTL coding in Verilog, Low-power design techniques

Jtag, Shell, Python, Tcl, scan compression, IEEE 1149.x, MBIST, DFT implementation methodology, IEEE 1687, DFT EDA tools, ATPG, hierarchical DFT methodologies, LBIST, automation and scripting skills