Translate requirements to design specification by working closely with system architects
Translate the design specification to optimal digital micro-architecture
RTL coding using Verilog and System Verilog
Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP
Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures
Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements
Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems
Meet power, performance and area goals by micro-architecture optimization
Work closely with DV team to develop test-plans
Front end implementation - Lint/CDC , synthesis, Timing constraint development
Work closely with DFT and PD teams for signoff
Support Silicon validation
Mentor junior design engineers
Minimum Qualifications:
BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute
10 years of relevant experience
Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture
Strong hands-on RTL coding experience and debugging skills
Digital Subsystem, clocking and full chip integration experience
Expertise in timing constraints development and critical path timing closure
Experience with silicon and software product development and understanding the product development lifecycle
Knowledge of industry standard bus protocols such as AHB, APB, AXI
Experience in digital signal processing and Matlab modeling is highly desirable
Excellent verbal and written communication skills to work effectively with teams spread geographically
