Digital Logic Design, Scripting, RTL Coding, Clock domain crossing analysis, Lint checks, Static-timing-analysis, ECO flows

Logic Design, Verilog, Sta, Synthesis, block and top-level timing constraints, Power product design, mixed signal integrated circuits, Scan Insertion, Timing Analysis, design constraints, ATPG generation, synthesis scripts, RTL Coding, micro-architecture, System-Verilog