Staff DFT Engineer
Search Jobs
Search by job, company or skills
Search by job, company or skills
(www.enchargeai.com
Staff DFT Engineer
The 10 Hottest Semiconductor Startups Of 2025 (So Far)
https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-farpage=1
1
https://www.enchargeai.com/blog/the-efficiency-imperative-energy-will-define-ais-next-chapt
er
Location: Greater Bengaluru Area (Hybrid-2 days office,3 days-home) or Remote (any where in I
ndia
About Com
pany:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today's best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI sys
tems.
Developing silicon for Edge Computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote enviro
nments.
As the Design for Test (DFT) Senior staff, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge dep
loyment.
Key Respons
ibilitiesArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, a
nd MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge dat
a centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and
Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and p
ower impact.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimi
ze test time.
Technica
l RequirementsExperience: 7-10 years in DFT, with at least 2 years in a leadership or p
rincipal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or
Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan
(IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm
, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial fo
r edge
effi
ciency.
ContactUdaymuda
[Confidential Information]
mMulya Technologies'Mining the K
nowledge Community'Job ID: 151545407
Skills:
DFT verification, MBIST insertion, EDA Tools, Fault Simulation, Pattern generation
Skills:
logic bist , Scan Insertion, Multi-voltage power-gated designs, Boundary scan IEEE 1149.1, FinFET nodes 7nm 5nm or below, Transition Path Delay, MBIST, Synopsys TestMAX, Scan compression, Siemens Mentor Tessent, DFT architecture, ATPG, Cadence Modus, Hierarchical DFT, Stuck-at
Skills:
Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair
Skills:
Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis
Skills:
Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Cadence, Mentor, TetraMax, AMBA, Gate level simulations, Synthesis, ATPG, Digital RTL coding, Synopsys, PMIC
