STAFF DFT Engineer
STAFF DFT Engineer
Broadcom- Posted an hour ago
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Job Description
Job Description:
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.
Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.
The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills.
Educational qualification & Experience Level : Bachelor's degree with 8+ years of relevant experience or Master's degree with 6+ years of relevant experience
R027605
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.
Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.
The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills.
Educational qualification & Experience Level : Bachelor's degree with 8+ years of relevant experience or Master's degree with 6+ years of relevant experience
R027605
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Key Skills
About Company
Skills:
automation, Scripting, scan compression, BSCAN, MBIST, Siemens Tessent, SSN TestKompress, DFT architecture, ATPG, EDA Tools, Synopsys TetraMAX, DFTMAX, LBIST, IJTAG
Skills:
Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair
Skills:
C, Vcs, Tcl, Verilog, Jtag, Python, Perl, Synopsys Tetramax, MBIST, EDA Tools, Mentor Tessent, Verdi, DFT micro-architecture, Scan
Skills:
ATPG (Automatic Test Pattern Generation), logic bist , test coverage , Memory BIST (MBIST), DFT architecture, Digital DFT, Scan compression, SoC MCU architecture, DFT protocols, Debug effort
Skills:
Python, Clp, Tcl, Perl, JTAG BSCAN, MBIST, LEC, SoC DFT Architecture, Logic and DRC analysis, P1500 implementation, ZERO delay and SDF based scan, ATPG DRC analysis, Memory BIST implementation, Hybrid-TK Compression, LPCT, Stuck at TDF, Scan Insertion, power analysis methodologies, Test coverage debug, JTAG simulations, Bridging Cell-aware iddq fault models, LBIST, iJTAG