DFT verification, MBIST insertion, EDA Tools, Fault Simulation, Pattern generation

logic bist , Scan Insertion, Multi-voltage power-gated designs, Boundary scan IEEE 1149.1, FinFET nodes 7nm 5nm or below, Transition Path Delay, MBIST, Synopsys TestMAX, Scan compression, Siemens Mentor Tessent, DFT architecture, ATPG, Cadence Modus, Hierarchical DFT, Stuck-at

Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Cadence, Mentor, TetraMax, AMBA, Gate level simulations, Synthesis, ATPG, Digital RTL coding, Synopsys, PMIC

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis