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STA Lead
Location: Bengaluru, India
Experience: 6–10 Years
Role Overview
We are seeking a highly skilled STA Lead to drive timing closure and signoff for complex SoC, CPU, AI/ML, and high-performance computing designs at advanced technology nodes. This is a hands-on technical role focused on timing analysis, signoff quality, methodology development, and achieving first-pass silicon success.
Key Responsibilities
Required Skills & Qualifications
Preferred
Join us to solve challenging timing problems and enable the next generation of high-performance semiconductor products.
Job ID: 150873175
Skills:
AOCV POCV SOCV analysis, Monte Carlo simulations, Yield Analysis, Timing Closure, IR drop analysis, Timing Marginings
Skills:
DMSA full chip and custom scripts for timing fixes, Pre Post-layout constraint development, IP level constraint integration, Tempus, RC Balancing and scaling analysis of critical data paths, RC C model selection understanding, primetime, Abstraction expertise like Hyperscale ILM ETM, RC Balancing and scaling analysis of full chip clock, EDA tool-specific scripting, STA timing closure methodologies, Multi-voltage Switching aware corner definitions
Skills:
synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking
Skills:
Perl scripting, Synthesis, Physical Design, primetime, Functional and DFT modes, Flow automation, SoC design and implementation methodology, Constraint development, Digital ASIC design
Skills:
Synthesis Flow setup, Tempus flows, LEC flow setup, Genus flows, Synthesis flows, STA timing ECOs, STA flow setup, Constraints clocks, timing convergence, STA flows, Post-Scan Synthesis netlist, STA timing checks
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