AOCV POCV SOCV analysis, Monte Carlo simulations, Yield Analysis, Timing Closure, IR drop analysis, Timing Marginings

DMSA full chip and custom scripts for timing fixes, Pre Post-layout constraint development, IP level constraint integration, Tempus, RC Balancing and scaling analysis of critical data paths, RC C model selection understanding, primetime, Abstraction expertise like Hyperscale ILM ETM, RC Balancing and scaling analysis of full chip clock, EDA tool-specific scripting, STA timing closure methodologies, Multi-voltage Switching aware corner definitions

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking

Perl scripting, Synthesis, Physical Design, primetime, Functional and DFT modes, Flow automation, SoC design and implementation methodology, Constraint development, Digital ASIC design

Synthesis Flow setup, Tempus flows, LEC flow setup, Genus flows, Synthesis flows, STA timing ECOs, STA flow setup, Constraints clocks, timing convergence, STA flows, Post-Scan Synthesis netlist, STA timing checks

Python, Tcl, primetime, Dft, PT-DMSA, timing congestion, ECO generation flow, IO Timing interface budgeting, ASIC timing constraints generation

Routing, Perl scripting, Physical Synthesis, Multi voltage design convergence, primetime, Optimization, CTS, Floor-planning, Deep sub-micron design problems, Tempus, Clocking architecture, Placement, Crosstalk avoidance, Constraint generation and validation, Power Estimation, Clock Tree Synthesis, High frequency Datapath intensive Cores

PERL, Static Timing Analysis, Tcl, SDC constraints, primetime, Place and route methodologies, Tk, Manual timing fixes ECO generation, Tempus, DMSA Tweaker ECO flows