STA engineer
STA engineer
Mirafra TechnologiesThis job is no longer accepting applications
Job Description
Key Responsibilities
- Constraint Development & Validation: Create, validate, and manage SDC constraints (clocks, I/O paths, generated clocks, false/multicycle paths) to accurately reflect the design's intent.
- Timing Analysis & Closure: Run full-chip and block-level STA using sign-off tools like Synopsys PrimeTime or Cadence Tempus.
- Constraint QoR Checks: Evaluate and debug timing reports to fix setup, hold, and DRC (Design Rule Checking) violations.
- Cross-Domain Analysis: Perform Clock Domain Crossing (CDC) analysis and manage constraints for asynchronous crossings.
- ECO Execution: Drive Engineering Change Orders (ECOs) by partnering with Physical Design (PD) and RTL teams.
- Scripting: Develop scripts using Tcl, Perl, or Python for automation and workflow efficiency.
Qualifications
- Education: B.Tech/M.Tech in Electrical or Electronics Engineering.
- Tools: Strong working knowledge of standard industry tools (PrimeTime, Tempus).
Experience: 4-10+ years
More Info
Job Type:
Industry:
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Employment Type:
Key Skills
DRC Design Rule Checking
ECO Execution
SDC constraints
timing reports
Clock Domain Crossing CDC analysis
Cadence Tempus
About Company
Skills:
Static Timing Analysis (STA), Timing ECO strategies, Full-Chip Timing Closure
Skills:
synopsys primetime , Perl, Static Timing Analysis, Python, Tcl, Timing exceptions, OCV, ASIC implementation, Full-chip STA, Timing sign-off, Timing Closure, SDC, MMMC, POCV, Si, Physical design flow, AOCV
Skills:
Clp, automation, Scripting, LINT, prelayout STA, low power aspects, postlayout STA, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking
Skills:
Chip Level STA, Pt, Prime clouser
Skills:
Sta, RTL2GDS, physical design EDA tools, Cadence, Synopsys, Synopsis Primetime