low power design, Sta, Block and SoC level Synthesis, Block and SoC level equivalence check, Block and SoC level timing convergence, Timing ECO generation

synopsys primetime , Python, Tcl, PrimeTime-PX, PrimeTime-SI, POCV, crosstalk analysis, MCMM timing analysis, Cadence Tempus Timing Signoff Solution, AOCV

synopsys tools , .lib generation, python, perl, Tcl, STA tools, PD circuit simulation, ICC2

Timing ECO Implementation, LVF POCV variation formats, digital design Implementation, RTL to GDSII, Timing Analysis, Timing Closure, CTS strategies, STA setup, Cadence Tools, Tweaker Prime Time based ECO flows, Automation scripts, Constraint development

RTL2GDS, physical design EDA tools, Sta

STA Engineer, constraint development

Sta, RTL2GDS, EDA Tools, Timing Analysis, Physical Design

Perl, Static Timing Analysis, Python, Tcl, OCV, primetime, SI Crosstalk, CRPR, Cadence Tempus, SDC, Eco, MMMC, POCV, AOCV

Sta, GLS, post-layout STA, Synthesis, SDF generation, LINT, LEC, cdc, primetime, Tempus, MMMC analysis, ETM timing model validation, Timing Closure, SDC constraints development, Dft