Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, SDC knowledge, Fishtail, GCA, Synopsys Design Compiler, DMSA

Synthesis Flow setup, Tempus flows, LEC flow setup, Genus flows, Synthesis flows, STA timing ECOs, STA flow setup, Constraints clocks, timing convergence, STA flows, Post-Scan Synthesis netlist, STA timing checks

Python, Tcl, PVT corner definition, primetime, Synopsys STA tools, PTPX, extraction corners, margining, POCVM, MCMM, AOCV, LVF

Tcl Scripting, Sta, OCV, CTS extraction, primetime, Tempus, ECO closure, ASIC SoC designs, timing exception validation, MMMC, advanced technology nodes, POCV, Setup Hold, Si, timing signoff, SDC constraints, IR-drop, CRPR, physical design impacts on timing, Subsystem block-level timing signoff, crosstalk, low-power UPF, Timing Closure, AOCV

synopsys primetime , Static Timing Analysis, low-power timing checks, post-layout STA, setup hold analysis, timing signoff SI analysis, ASIC SoC physical design flow, ECO support, Timing Closure, path-based timing analysis, timing constraints validation, signoff activities, clock analysis

rc extraction , C, Unix Shell, routing, PERL, Scripting, Linux, Tcl, functional ECOs, low power implementation methods, timing optimization, Power Planning, formal verification, debugging timing violations, IR drop analysis, timing fixes, Physical Design Flow, floorplanning, cross talk, GPU cores, Signal Integrity, Placement, noise and delay analysis, Clock Tree Synthesis

Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, Fishtail, SDC knowledge, GCA, Synopsys Design Compiler, DMSA

Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, Fishtail, SDC knowledge, Synopsys Design Compiler, GCA, DMSA

Sta, Synopsys, Synopsis Primetime, RTL2GDS, physical design EDA tools, Cadence