Position: STA Engineer
Experience: 7+ Years (Preferred: Intel project experience)
Location: Bangalore
Availability: Immediate to 30 Days
Job Description:
- 7+ years of STA and timing closure experience on ASIC/SoC designs.
- Strong expertise in Setup/Hold, MMMC, OCV/AOCV/POCV, CRPR, SI, and timing signoff.
- Hands-on experience with SDC constraints, timing exception validation, and ECO closure.
- Proficient in PrimeTime/Tempus and Tcl scripting.
- Experience in Subsystem/block-level timing signoff and advanced technology nodes.
- Good understanding of CTS, extraction, IR-drop, crosstalk, low-power (UPF) and physical design impacts on timing.
- Prior Intel project experience preferred.
