STA Engineer
STA Engineer
ambit semiconductors inc4-6 Years
- Posted 16 days ago
- Be among the first 10 applicants
Job Description
We're Hiring: STA Engineer – Bangalore
Are you passionate about timing closure and signoff for complex ASIC/SoC designs Join our team and make an impact!
Job Description:
- Driving STA and timing closure across advanced technology nodes
- Performing Setup/Hold analysis, MMMC, OCV/AOCV/POCV, CRPR, SI, and timing signoff
- Validating SDC constraints, timing exceptions, and ECO closure
- Collaborating on subsystem/block-level timing signoff
- Partnering with physical design teams on CTS, extraction, IR-drop, crosstalk, and low-power (UPF) impacts
Requirement:
- 4+ years of STA experience in ASIC/SoC designs
- Strong hands-on expertise with PrimeTime/Tempus and Tcl scripting
- Solid understanding of timing closure methodologies and signoff flows
- Prior Intel project experience is a big plus!
Location: Bangalore
More Info
Job Type:
Industry:
Employment Type:
Key Skills
Timing exceptions
SDC constraints
CTS extraction
Crosstalk
IR-drop
Tempus
ECO closure
Setup Hold analysis
Low-power UPF impacts
CRPR
MMMC
POCV
Timing signoff
AOCV
About Company
Skills:
primetime, timing signoff tools, Functional and Test Mode constraints merging, constraints development, Timing Closure, OCV timing corners, Tempus, Group and Path based analysis, IO STA, ILM timing models, Crosstalk analysis
Skills:
synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff
Skills:
Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus
Skills:
Synopsys Design Constraints (SDC), Multi-Mode Multi-Corner (MMMC) timing analysis, On-Chip Variation (OCV), Static Timing Analysis (STA), IR-drop aware STA, Mentor Graphics
Skills:
monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis