primetime, timing signoff tools, Functional and Test Mode constraints merging, constraints development, Timing Closure, OCV timing corners, Tempus, Group and Path based analysis, IO STA, ILM timing models, Crosstalk analysis

synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff

Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus

Synopsys Design Constraints (SDC), Multi-Mode Multi-Corner (MMMC) timing analysis, On-Chip Variation (OCV), Static Timing Analysis (STA), IR-drop aware STA, Mentor Graphics

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis

Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, AI scripting, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Fisthail, Timing Closure, Synthesis, Excellicon, Postlayout STA, Timing Constraints, TCM

Clp, Automation, SDC constraints development, Synthesis, Timing Closure, LINT, LEC, AI scripting, Prelayout STA, cdc, Postlayout STA, RTL Netlist based static checks, SDC generation

Perl, Python, Tcl, Timing ECO generation, Sta, Block and SoC level Synthesis, Block and SoC level equivalence check, primetime, Block and SoC level timing convergence, Tempus

STA engineer, Synthesis, Dft