Lead STA Engineer (Full-Chip)

Lead STA Engineer (Full-Chip)

Location: Bangalore

Experience: 8+ Years

Job Description:

We are looking for an experienced Lead STA Engineer with strong expertise in full-chip Static Timing Analysis (STA) and hands-on experience with Cadence tools. The candidate will be responsible for timing analysis, constraint development, timing closure, and optimization of complex SoC designs.

Key Responsibilities:

• Perform full-chip STA across multiple PVT corners and timing modes.
• Develop, validate, and debug SDC timing constraints.
• Analyze setup, hold, recovery, removal, and clock-related timing violations.
• Drive timing closure through collaboration with Physical Design, Synthesis, and RTL teams.
• Perform timing ECOs and optimize critical paths.
• Debug SI, crosstalk, and signal integrity-related timing issues.
• Generate and review timing reports to ensure design meets performance targets.

Must-Have Skills:

• 8+ years of hands-on experience in Static Timing Analysis (STA).
• Strong experience in full-chip STA and timing closure.
• Hands-on experience with Cadence Tempus.
• Strong knowledge of SDC constraints, MMMC, MCMM, and timing analysis.
• Experience with setup/hold analysis, timing ECOs, and timing optimization.
• Good understanding of STA fundamentals, clocking, and signal integrity.