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Job ID: 148999879
Skills:
Ovm, Tcl Scripting, Perl, Verilog, automation, Specman, SV, assertions development, functional and code coverages, RTL, Uvm, SDF sim debug, GLS, formal verification, eRM methodology, test-bench development, closure constraint randomization, HVL
Skills:
Verilog, Pcie, Debugging, Rtl Design, systemverilog, Uvm, CXL, PXC, Vlsi, Digital Design, SoC Verification
Skills:
code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL
Skills:
testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog
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