Ovm, Tcl Scripting, Perl, Verilog, automation, Specman, SV, assertions development, functional and code coverages, RTL, Uvm, SDF sim debug, GLS, formal verification, eRM methodology, test-bench development, closure constraint randomization, HVL

Verilog, Pcie, Debugging, Rtl Design, systemverilog, Uvm, CXL, PXC, Vlsi, Digital Design, SoC Verification

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog