debugging complex IP designs, UVM methodology, test plan reviews, testbench development, systemverilog

System Verilog, Uvm, Environment Development, Design Verification, Functional Verification, Test Plan Generation

Ovm, automation, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification