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• IP verification Using SV/UVM
• SOC Verification using C/SV
• Third Party VIP Integration
• Interconnect Protocols: AHB, AXI, APB
• SOC Interfaces: GPIO, SPI, I2C, UART (4+)
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
• Memory Interfaces: DDR or HBM I/O (10+)
• Coverage Closure: Code, Functional and Toggle
• Tools: Synopsys VCS or Cadence Incsive
• Technical Documentation: Testbench Specification, Test Plan Specification
• Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3000+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.
Job ID: 104666491
Skills:
Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi
Skills:
code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL
Skills:
python, perl, SV test benches, Gate level simulations, SDF annotation, VMM, constrained random verification, Uvm, functional coverage, C-reference models
Skills:
automation, Ovm, Tcl Scripting, Verilog, Perl, test-bench development, GLS, Uvm, RTL, SV, SDF sim debug, Specman, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification
Skills:
automation, Ovm, Tcl Scripting, Verilog, Perl, Uvm, GLS, RTL, SV, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification
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