Sr analog design Engineer

Job Summary:

We are seeking a highly skilled Sr Analog Design Engineer with hands-on experience in high-speed SerDes (Serializer/Deserializer) PHY. The ideal candidate will have a strong background in Analog SerDes PHY Design, familiarity with analog front-end circuits such as CTLE, VGA, Summer, CDR, and PAM4-based TX, equitation algorithms and exposure to ADC-based PAM4 architectures is a strong plus.

Key Responsibilities:

Design and develop high-speed analog circuits for SerDes interfaces (including TX and RX paths).
Architect and implement PAM4-based transmitters and receivers, ensuring compliance with industry standards.
Contribute to the development of CTLE (Continuous-Time Linear Equalizer), VGA (Variable Gain Amplifier), Summer, and Clock and Data Recovery (CDR) circuits.
Collaborate with digital and mixed-signal teams on ADC-based PAM4 solutions.
Analyze and model system-level behaviour using equitation algorithms for performance optimization.
Conduct pre- and post-layout simulations, behavioural modelling, and design reviews.
Work closely with layout engineers to ensure optimal layout implementation.
Validate and debug silicon in the lab; perform correlation with simulation results.
Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering or related field.
5+ years of experience in analog/mixed-signal design, specifically in SerDes and high-speed data interfaces.
Strong hands-on experience with:
PAM4 SerDes design
CTLE, VGA, Summer, CDR, PAM4 TX
Equitation algorithms
Familiarity with ADC-based PAM4 architecture and digital calibration techniques is an advantage.
Proficiency in EDA tools (Cadence Virtuoso, Spectre, HSPICE, MATLAB, etc.).
Solid understanding of signal integrity, jitter, and noise analysis.
Preferred Skills:

Experience in silicon validation, lab testing, and high-speed measurements.
Knowledge of industry standards such as IEEE 802.3, PCIe, or USB.
Excellent problem-solving skills and ability to work in a fast-paced team environment.