Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
Experience with EDA tools for schematic entry, physical layout, and design verification.
High proficiency with spice simulators including HSPICE, Finesim and XA
Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture.
Plus Qualifications:
Ability to provide automation for rapid and dynamic design needs is highly sought-after
Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart
Experienced in STAR or similar extractor to debug extraction issues
Extensive programming skills in languages such as Python, Perl, TCL and C/C++
