Silicon Networking RTL Design Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
• Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
• Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control, etc.

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl).
• Experience in SoC designs and integration flows.
• Knowledge of high performance and low power design techniques.
• Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.

Responsibilities

• Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain.
• Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications. 
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Identify and lead power, performance, and area improvements for the domains owned.