power analysis, DDR testing methodologies, verification flow, debug validation, STA simulation, IR-drop mitigation, spyglass, Ate, Dft, Tessent, SERDES, patterns generation, Timing Closure, silicon bring-up, ASIC DFT synthesis, Synopsys

Machine learning (ML) SoCs, Soc Architecture, ASIC design flows, Power/performance/area tradeoffs, RTL integration, Hardware/software interface optimization