Senior Staff DFT Engineer
encharge ai- Posted 7 days ago
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Job Description
(www.enchargeai.com)
Senior Staff DFT Engineer
The 10 Hottest Semiconductor Startups Of 2025 (So Far)
https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-farpage=1
1
https://www.enchargeai.com/blog/the-efficiency-imperative-energy-will-define-ais-next-chapt
er
Location: Greater Bengaluru Area (Hybrid-2 days office,3 days-home) or Remote (any where in I
ndia
About Com
pany:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today's best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI sys
tems.
Developing silicon for Edge Computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote enviro
nments.
As the Design for Test (DFT) Senior staff, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge dep
loyment.
Key Respons
ibilitiesArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, a
nd MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge dat
a centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and
Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and p
ower impact.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimi
ze test time.
Technica
l RequirementsExperience: 10-14 years in DFT, with at least 2 years in a leadership or p
rincipal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or
Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan
(IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm
, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial fo
r edge
effi
ciency.
Contact
Uday
mud[Confidential Information]
Mulya Technologies
Mining the Knowledge Community
More Info
Key Skills
Multi-voltage power-gated designs
Synopsys TestMAX
Scan compression
Siemens Mentor Tessent
DFT architecture
Cadence Modus
Hierarchical DFT
Stuck-at
MBIST Memory Built-In Self-Test with repair capabilities
Path Delay
In-System Test (IST)
Power-on self-test (POST)
About Company
