Job Title: Senior STA Engineer
Experience: 612 Years
Location: Bangalore
Job Summary
We are seeking an experienced
STA Engineer with strong hands-on expertise in
sub-system level timing analysis and closure. The ideal candidate will drive timing convergence across multiple integrated blocks within a subsystem and ensure clean timing signoff across all MMMC scenarios, ensuring full tapeout readiness.
Key Responsibilities
- Drive sub-system level STA and hierarchical timing closure across multiple integrated blocks
- Develop, validate, and maintain SDC constraints at the sub-system level
- Perform MMMC timing analysis including setup, hold, recovery, and removal checks
- Analyze and close timing violations including setup, hold, and cross-domain paths
- Debug complex timing paths such as multi-cycle paths, false paths, and CDC interactions
- Handle OCV/AOCV/POCV modeling and derate analysis
- Perform SI-aware timing analysis and assess noise impact
- Validate timing budgets and ensure interface timing alignment
- Support low-power timing verification including multi-voltage and power domain analysis
- Collaborate with Physical Design (PD) teams for timing ECO implementation and closure
- Participate in timing signoff reviews and support tapeout readiness activities
Required Technical Skills
- Strong expertise in PrimeTime or Tempus for signoff timing analysis
- Deep understanding of MMMC concepts and corner analysis
- Strong knowledge of OCV / AOCV / POCV modeling
- Experience in crosstalk and signal integrity (SI) analysis
- Experience working on multi-clock and multi-voltage domain designs
- Strong understanding of clock gating and generated clocks
- Hands-on experience in sub-system or hierarchical timing closure
- Strong debugging capability for critical and complex timing paths
- Good understanding of synthesis and physical design impact on timing
- Proficiency in Tcl scripting for automation and report analysis
