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Senior RTL Design Engineer
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LLTS is looking to hire for RTL design engineers with 6+ years of experience with below skills set ::
RTL Design Engineer with 6+ of Hands on experiences.
• Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL) , IP Design, SoC Design and Integration
• Should have hands on experience in all the Design aspects, should work independently.
• Experience/proficiency in front-end (logic) design of large complex high-speed digital stems from Specification to RTL code signoff
• Experience on RTL signoff tools, Lint, CDC, FE BE, Equivalence checks, Spyglass and other equivalent tools
• Strong team player & effective in communication
Job ID: 153641795
Skills:
Vcs, Shell, Pcie, Verilog, Scripting Languages, Python, Perl, LINT, cdc, Design Compiler, RTL for area and power reduction, C Language, Low power estimation, Low power RTL design, Floating point datapath design, Arithmetic units, optimization of microarchitecture, Rtl Design, ASIC design tools, Synthesis, Verdi, PTPX, spyglass, Timing Closure, Microarchitecture, CXL, power estimation tools
Skills:
Verilog, System Verilog, Cadence JasperGold, digital-analog interface, UPF, LEC, clock gating, Linting, PIPE interface standard, high-speed SerDes architectures, formal verification, calibration algorithms, Synopsys SpyGlass, low-power design techniques
Skills:
Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog
Skills:
Usb, Verilog, Ethernet, Pcie, DDR, VHDL, UCIe, LINT, systemverilog, cdc, Sta, Synthesis, formal checking, HBM, RDC, spyglass
Skills:
rtl development , Fpga, hardware design tools, LINT, front end design flow, ASIC, RTL Netlist, cdc, RTL Coding
