Vcs, Shell, Pcie, Verilog, Scripting Languages, Python, Perl, LINT, cdc, Design Compiler, RTL for area and power reduction, C Language, Low power estimation, Low power RTL design, Floating point datapath design, Arithmetic units, optimization of microarchitecture, Rtl Design, ASIC design tools, Synthesis, Verdi, PTPX, spyglass, Timing Closure, Microarchitecture, CXL, power estimation tools

Verilog, System Verilog, Cadence JasperGold, digital-analog interface, UPF, LEC, clock gating, Linting, PIPE interface standard, high-speed SerDes architectures, formal verification, calibration algorithms, Synopsys SpyGlass, low-power design techniques

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

Usb, Verilog, Ethernet, Pcie, DDR, VHDL, UCIe, LINT, systemverilog, cdc, Sta, Synthesis, formal checking, HBM, RDC, spyglass

rtl development , Fpga, hardware design tools, LINT, front end design flow, ASIC, RTL Netlist, cdc, RTL Coding