Senior RTL Design Engineer
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Hi All,
Job Location: Bangalore
Notice Period: 15 days to 30 Days
Minimum: 5+ Years
1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
4. Experience with hardware architecture exploration, performance modelling will be a big plus.
5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
6.Must have experience in Lint and CDC.
7.Must have RTL Design worked on PCIe/CXL
Thanks,
K Himabindu
Job ID: 153632925
Skills:
Integration, Verilog, FE, LINT, cdc, BE, RTL signoff tools, RTL IP Design, Rtl Design, spyglass, VHDL, hardware description, SOC design, front-end logic design, Equivalence checks
Skills:
Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc
Skills:
Verilog, System Verilog, Cadence JasperGold, digital-analog interface, UPF, LEC, clock gating, Linting, PIPE interface standard, high-speed SerDes architectures, formal verification, calibration algorithms, Synopsys SpyGlass, low-power design techniques
Skills:
Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog
Skills:
Usb, Verilog, Ethernet, Pcie, DDR, VHDL, UCIe, LINT, systemverilog, cdc, Sta, Synthesis, formal checking, HBM, RDC, spyglass
