Search Jobs
Search by job, company or skills
Search by job, company or skills
Job Location: Bangalore
Notice Period: 15 days to 30 Days
Minimum: 5+ Years
1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
4. Experience with hardware architecture exploration, performance modelling will be a big plus.
5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
6.Must have experience in Lint and CDC.
7.Must have RTL Design worked on PCIe/CXL
Job ID: 144764867
Skills:
Verilog, System Verilog, PIPE interface standard, calibration algorithms, clock gating, high-speed SerDes architectures, Linting, digital-analog interface, LEC, UPF, Synopsys SpyGlass, formal verification, Cadence JasperGold, low-power design techniques
Skills:
DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB
Skills:
Verilog, RDC, LINT, ISO 26262, Safety analysis methodologies, Functional Safety concepts, RTL design and integration, systemverilog, ASIL requirements, Synthesis checks, cdc, Micro-architecture development
Skills:
Usb, DDR, Pcie, Verilog, Ethernet, LINT, Sta, Synthesis, cdc, UCIe, systemverilog, spyglass, VHDL, formal checking, RDC, HBM
Skills:
MATLAB, Verilog, Python, DVB-S2, PSK, DSP Algorithms, JESD204B C, BCH, LDPC, ADC DAC architectures, Vivado, SDR Architectures, FPGA Development, VHDL, QPSK, RF Systems, Xilinx, Rtl Design, DVB-S2X
We don’t charge any money for job offers
