Senior RTL Design Engineer
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Job Location: Bangalore
Notice Period: 15 days to 30 Days
Minimum: 5+ Years
1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
4. Experience with hardware architecture exploration, performance modelling will be a big plus.
5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
6.Must have experience in Lint and CDC.
7.Must have RTL Design worked on PCIe/CXL
Job ID: 144764867
Skills:
AMBA protocols - AXI AHB APB, Verilog, LINT, cdc, ECO fixes, Logic design RTL coding, Asynchronous interface, Synthesis, formal verification, SoC clocking reset architecture, SoC design and integration, Multi Clock designs, System-Verilog
Skills:
telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts
Skills:
Ovm, Python, Perl, power management techniques, Uvm, verification methodologies, Timing Analysis, systemverilog, digital hardware design, static design checks, cdc, Linting, Verilog Hdl, design specifications, physical implementation, Synthesis, Dft, RDC, X-Propagation
Skills:
Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design
Skills:
rtl development , Fpga, hardware design tools, LINT, front end design flow, ASIC, RTL Netlist, cdc, RTL Coding
