rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Computer Architecture, Timing Constraints, digital RTL design, RTL microarchitecture, architecture experience on advanced SoCs, clocking and reset methodologies

telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts, Mentor Graphics, Cadence, Synopsys